module counter_8bit (
    input clk,
    input reset_n,
    input enable,
    `ifdef PRO_FPGA
    input [7:0] sys_id,
    `endif
    output reg [7:0] count,
    output overflow
);

// 参数定义
parameter MAX_COUNT = 8'hFF;
parameter MIN_COUNT = 8'h00;
parameter RESET_VALUE = 8'h00;

// 内部信号
wire reset_sync;
wire enable_sync;
reg count_en;

// 复位同步
assign reset_sync = ~reset_n;
assign enable_sync = enable;

// 计数逻辑
always @(posedge clk or posedge reset_sync) begin
    if (reset_sync) begin
        count <= RESET_VALUE;
        count_en <= 1'b0;
    end else begin
        count_en <= enable_sync;
        if (enable_sync) begin
            if (count == MAX_COUNT)
                count <= MIN_COUNT;
            else
                count <= count + 1'b1;
        end
    end
end

// 溢出检测
assign overflow = (count == MAX_COUNT) && enable_sync;

endmodule